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An implementation is described for eliminating cycles lost due to a current machine design of disabling overlap of instruction decoding and execution for decimal instructions.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
79% of the total text.
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Performance Enhancement for Decimal Instructions
An implementation is described for eliminating cycles lost due to a current
machine design of disabling overlap of instruction decoding and execution for
In some high-performance computers, overlap of decimal instruction
execution and decoding of a subsequent instruction is disabled. Overlap is
disabled because source and destination operand fetches are controlled by a
micro-coded execution unit with no interaction with the instruction unit to detect
conflicts for hardware usage in the instruction unit. Therefor, the instruction unit
cannot be enabled for further decoding until the execution unit has completed the
decimal instruction. The key to leaving overlap enabled for decoding subsequent
instructions is to cause the instruction unit to have control of source and
destination operand fetching, store an indication of decimal execution in process,
and use two count registers not previously used for decimal instructions, but
used for variable-length logical instructions.
A new instruction can be decoded while a decimal instruction is being
executed if: 1. during the prefetching of decimal operands it is determined that
the next instruction does not require a storage access (i.e. a simple RR
arithmetic instruction), or 2. the subsequent instruction to be decoded requires a
storage access, and the last decimal fetch is initiated by the instruction unit, as
indicated by the count registers.