Virtual Address Translation Speedup Circuitry
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
The virtual address translation speedup circuitry is an improvement ove the speedup circuitry in U. S. Patent 4,170,039. The virtual address to be translated is contained in virtual address register 10. The virtual address includes bits 1-P inclusive. Of these bits, bits M-N are used as an address for simultaneously addressing translation tables 20 and 30. Tables 20 and 30 contain address translation candidates and associated main storage addresses.