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Direct Coupled OR Gate

IP.com Disclosure Number: IPCOM000052649D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Mukherjee, A [+details]

Abstract

A direct coupled OR gate suitable for use in Josephson circuitry is described which has good noise immunity and which can support a parallel fanout of 3. The circuit comprises an isolator stage P and a buffer stage Q. Inputs are provided through impedances Z(in) to isolator stage P, which comprises Josephson devices J(1) and J(2). The buffer stage Q is comprised of Josephson tunneling devices J(3) and J(4). An electrical interconnection is made between node A in stage P and node C in stage Q. This connection allows transfer of the full gate current from stage P to stage Q when the inputs switch isolator stage P.