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Integration of High Performance Vertical PNP and NPN Transistors

IP.com Disclosure Number: IPCOM000052650D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Isaac, RD Ning, TH Tang, DD [+details]

Abstract

A compatible process is described for integrating vertical pnp and npn transistors, with specific application to MTL (Merged Transistor Logic).