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Run Scan Synch Circuit for Josephson Logic Chips

IP.com Disclosure Number: IPCOM000052653D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Herrell, DJ [+details]

Abstract

In Josephson logic technology, as well as in other logic technologies, circuit is required which will control the logic operation as to its normal operation (RUN) and level sensitive scan detection (LSSD) loading and unloading (SCAN). This circuit controls the RUN and SCAN operations for either a single-cycle operation (SCO) or a multiple-cycle operation (MCO).