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Shown in Fig. 1A is a four-phase overlap clock ring counter. This counter, which is self-cleaning, comprises a shift register and NAND gates for feeding back its input.
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Four Phase Overlap Clock Ring Counter
Shown in Fig. 1A is a four-phase overlap clock ring counter. This counter,
which is self-cleaning, comprises a shift register and NAND gates for feeding
back its input.
Four overlap clock pulses R, S, T, U, as shown in Fig. 1B, are provided for
the counter. To get a delay of 50 nanoseconds in the propagation of information
within the shift register, each stage comprises four latches arranged in two pairs
of latches L1 and L2. Latches L1 and L2 are built according to the LSSD (level
sensitive scan design) technique, as described in Electronics, March 15, 1979,
page 108 and represented in Fig. 1C.
Latches L1 and L2 comprise NAND gates. The clock driver comprises two
inverters I, which from a clock C provide +C CLK and -C CLK signals for latch L1.
In the same way, +B CLK and -B CLK are applied from a clock B to latch L2.
In the first stage of the counter of Fig. 1A, the two first latches L1 and L2 are
actuated through clocks R and S and the two second latches L1 and L2 are
actuated through clocks T and U (acting as clocks B and C of Fig. 1C).
Each latch L1 and L2 has true and complement outputs +L1 and -L1, +L2
and -L2. In Fig. 1A, the complement -L1 and -L2 are referenced through an
arrow angle. An increment of a 12.5 ns delay will be available from one latch to
On this particular example four loops are provided, built as shown on Fig.
Depending upon the desired clock output, these four loops LP1 to LP4 are