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This article describes a communication discipline for a two-bit bus which interconnects two or more units. All bus contentions are automatically resolved, with priority, prior to the loss of any data.
English (United States)
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Two Bit Communication Discipline With Inherent Priority Contention
This article describes a communication discipline for a two-bit bus which
interconnects two or more units. All bus contentions are automatically resolved,
with priority, prior to the loss of any data.
The two-bit bus consists of a data bus and a control bus, each one bit wide.
Data is transmitted serially by bit synchronously with a clock common to all units
using the data bus. The control bus is used only to indicate the presence of data
on the data bus.
A unit does not begin transmission unless the control bus is inactive. When a
unit begins transmission, the control bus is made active by the sending unit(s)
and the address of the sending unit is transmitted on the data bus, starting with
the high-order bit. The data bytes, serial by bit, immediately follow the address.
When all data bytes have been transmitted, the control bus is allowed to go
As each bit of the address is transmitted, starting with the highest order bit,
the address bit intended is compared with the actual data on the bus. If an
unequal compare is detected, transmission is terminated immediately, because
another unit having higher priority was also transmitting.
Suppose the logic is such that a ""0'' signal clamps the data bus low and a
""]'' signal (in the absence of a ""0'') allows the data bus to go high. This means
address zero is the highest priority. Since an active control bus prevents other