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Browse Prior Art Database

Addressing Technique for Dynamic Memory

IP.com Disclosure Number: IPCOM000052851D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Davis, TH Eggebrecht, LC [+details]

Abstract

One technique for a memory architecture requires 16K bytes of unpaged memory and from 1 to 7 additional 16K-byte blocks of paged memory. This may be implemented by using, for example, an Intel 8202 dynamic random-access memory controller such as shown in the figure. Under normal circumstances the controller is capable of controlling 64K bytes of unpaged memory.