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Maximized LSSD Test I/O Pin Usage Disclosure Number: IPCOM000052855D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11

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Whitley, WP [+details]


This technique enables additional tests to be performed on an integrated circuit chip by means of the same chip I/O pins as are presently used for normal level sensitive scan design (LSSD) testing of the chip. This is done by providing multiplexing circuitry on the chip for enabling additional test points to be connected to one of the LSSD test I/O pins when LSSD tests are not being performed. Other existing LSSD I/O pins are used to control the multiplexing circuitry.