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Tighter Spacing of Metal Lines for Improved Density

IP.com Disclosure Number: IPCOM000052906D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Goth, GR Malaviya, SD Sarkary, HG [+details]

Abstract

The process starts by depositing polysilicon on top of a silicon wafer having a suitable passivation layer 2 previously formed thereon. A photoresist in as then used to form mask 3. Implantation of N/+/ (arsenic) through the mask is effected, as shown. The mask is then etched away, and the N/+/ activated. An oxide layer 4 is then grown differentially, as shown in Fig. 2, at approximately 850 degrees C.