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High Density Planar Metal Lands

IP.com Disclosure Number: IPCOM000052911D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Barson, F Ho, AP Horng, CT [+details]

Abstract

It is known that closely spaced metal lands, to shrink the size of bipolar transistors, may be achieved by using N+ polysilicon and etching, as will be described with regard to Figs. 1-4. As shown in Fig. 1, N+ polysilicon is applied over the transistor and is then etched away from the base and other unwanted regions. A CVD (chemical vapor deposition) oxide, such as SiO(2), is then deposited over the wafer, as shown in Fig. 2. Thereafter, a blanket RIE (reactive ion etching) is undertaken to remove the oxide everywhere except at the sides of the polysilicon, and then the polysilicon is removed. This is shown in Fig. 3.