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Method to Fabricate NPN Transistors Involving Totally Non-Critical Mask Registrations

IP.com Disclosure Number: IPCOM000052914D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-12

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Jambotkar, CG [+details]


A method is described for fabricating NPN bipolar transistors for integrated circuits. The main feature of the method is that it eliminates the need to register a mask in a critical manner relative to the patterns already created on wafer substrates during processing. In designing mask geometries, allowance is then no longer necessary for normal mask misregistrations. As a consequence, the NPN transistors require smaller chip area. Further, the electrical characteristics of the transistors also possess a tighter tolerance.