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Buried Gate Electrically Alterable Memory Device

IP.com Disclosure Number: IPCOM000052919D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Tsang, YL [+details]

Abstract

In many designs for electrically alterable (EA) memory devices, much of the area is occupied by the programming gate and floating gate overlap due to the requirement for higher capacitive coupling. In such designs, the respective gate materials are laid on planes parallel to the wafer surface. This type of topology would demand more surface area if higher coupling is needed [1,2]. To overcome this constraint, folding can be introduced in portions of the device to introduce area-saving vertical geometric features.