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Linear Time Speedup of Fault Diagnosis in Array Processors Disclosure Number: IPCOM000053027D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12

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Miranker, GS [+details]


A machine architecture, logic circuit, and test protocol is defined which allows identification of faulty processing elements (PEs) in an array processor in time proportional to processing element size not (PE size) x (no. of PEs).