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Non Overlapping Clock Generator Disclosure Number: IPCOM000053050D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12

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Cases, M Moore, VS Thoma, NG [+details]


A circuit is described for generating a set of non-overlapping clock signals with the capability of gating and/or selecting input clock signals. This implementation has the added features of relative low power dissipation and high performance for a given set of capacitive loadings.