Browse Prior Art Database

Non Overlapping Clock Generator

IP.com Disclosure Number: IPCOM000053050D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Cases, M Moore, VS Thoma, NG [+details]

Abstract

A circuit is described for generating a set of non-overlapping clock signals with the capability of gating and/or selecting input clock signals. This implementation has the added features of relative low power dissipation and high performance for a given set of capacitive loadings.