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LSSD Test Architecture

IP.com Disclosure Number: IPCOM000053066D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Moser, JJ [+details]

Abstract

The complex task of test generation for today"s very large-scale integration products has resulted in a design technique called Level Sensitive Scan Design (LSSD) where all sequential memory elements are connected as shift registers, in addition to operating as storage units for internally generated data. The shift-register mode of operation is utilized during test as an efficient means of initializing and monitoring internal logic values. One characteristic of LSSD products is the relatively long test times associated with loading and unloading data into and out of the sequential memory elements on the product. During test generation for LSSD products, each memory, called LSSD shift register latch (SRL), is treated as both an input and an output.