Browse Prior Art Database

Fast Multiply Circuit

IP.com Disclosure Number: IPCOM000053089D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Hitchcock, RB [+details]

Abstract

The apparatus herein shown and described will allow a multiply to take place in a time proportional to: (N(1) log(2) log(2)n) +N(2) (1) where n = the number of bits in the multiplier and multiplicand. N(2)= the number of logic levels in an adder. N(1)= the number of levels in a special multivalued logic circuit that performs k-level majority logic and k ". residues by using a matrix adder.