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Method for Making Lateral PNP Devices

IP.com Disclosure Number: IPCOM000053104D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Antipov, I [+details]

Abstract

In polycrystalline silicon base contact vertical NPN transistors, the spacing between emitters and polycrystalline silicon base contacts is defined by the silicon dioxide wall. By adding a few extra process steps, this type of silicon dioxide wall can also be used to define the space between the collector and emitter of a lateral PNP, thus allowing the making of narrow base width lateral PNPs. In addition, it will also reduce the emitter size of the lateral PNP below the minimum allowable image, thus reducing the area of the stray diode.