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PLA Logic Reduction Technique

IP.com Disclosure Number: IPCOM000053139D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Love, RD Rhodes, KE [+details]

Abstract

The programmed logic array (PLA) is well established in the prior art, and its principles are described, for example, in U.S. Patent 3,593,317. To make more efficient use of PLA integrated circuit chip areas, a PLA logic reduction technique is disclosed which makes use of several elementary logic reduction principles that result in a significant savings in the number of product terms required to implement a particular complex logic function. The technique has been automated for computer-assisted PLA design applications.