Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
The processor described in U. S. Patent 4,200,927 has the following mechanism to handle branches and instruction fetches: - Operand fetch requests, both from the decoder (IPPF) and the E-unit, have priority over an instruction fetch (I-fetch) request. - There are three instruction buffers, each four doublewords deep, and they contend for I-fetching according to a Least Recently Used (LRU) algorithm. - Following the decode of a conditional branch, the I-unit continues decoding instructions, in conditional mode, according to the guess as to the branch outcome (BC and BCR are predicted to fall through; BXLE, BXL, BCT and BCTR to be taken). - When the branch is resolved by the E-unit, only the I-buffer containing the correct branch path is kept, and the other I-buffer is released.