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This article describes high voltage driver circuits in which bootstrap capacitors and protect rings are used to improve the junction breakdown characteristics of at least one FET in each circuit.
English (United States)
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High Voltage FET Driver Circuits
This article describes high voltage driver circuits in which bootstrap
capacitors and protect rings are used to improve the junction breakdown
characteristics of at least one FET in each circuit.
Referring to Fig. 1, an input signal having a value in the range of 0 to Vm is
applied at an input terminal 10, which is connected directly to a polysilicon 1 gate
12 of an FET device 14. Input 10 is connected to a polysilicon gate 16 for device
14 through a bootstrap capacitor 18. In device 14, a depletion implant exists in a
portion of the region underlying gate 16. Gate 16 is tied to a protect ring or field
plate 20 which protects the drain junction of the FET device 14. The drain
terminal of FET device 14 is connected to a high voltage Vp. The source
terminal of FET device 14 serves as an output.
The upper terminal of bootstrap capacitor 18 is connected to a voltage-
clamping circuit consisting of an FET device 22 in which the gate and drain
terminals are tied together. A depletion implant exists in a portion of the channel
underlying the gate. The source junction of FET device 22 is protected by a
protect ring or field plate 26 tied to the source terminal. The drain terminal of
FET device 22 is connected directly to a voltage source which optimally produces
a voltage equal to 1/2 the peak voltage of the input signal or 0.5 Vm.
When the input is at ground, the upper terminal of the capacitor 18 will be
charged to a voltage one threshold level below 0.5 Vm. When the input signal
begins to rise, the voltage on the upper terminal of the charged bootstrap
capacitor 18 will also begin to rise, increasing the voltage on protect ring 20 and
gate 16 of FET device 14. Regardless of the value of the input voltage, the
voltage between the gates 12 and 16 of...