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Timing Circuit in Josephson Latching Logic Circuits

IP.com Disclosure Number: IPCOM000053208D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Klein, M [+details]

Abstract

Josephson latching logic circuits may sometimes require the inversion o logic signals within a chain of logic gates. Simple inversion is not possible in latching circuits, but timed inverter circuits have been designed for this purpose. Such circuits require as one input a timing signal that must arrive within some suitable time interval relative to the expected time of arrival of the logic input to the inverter. Such timing signals are generated by a combination of a timing signal source triggered by a power supply transition and a delay line designed to provide the required time of arrival. The required delay will often be large.