DC Josephson Flip Flop
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
A DC flip-flop circuit, suitable as a latch circuit in a Josephson memory array, is designed without a third faulty stable state. D1 and D2 are three-junction Josephson interferometers, one of which receives the SET signal as a control signal, while the other receives the RESET signal as a control signal. An inductance L(D) is located in the current storage loop, and a damping resistor R(D) is provided. A series circuit, comprising inductance L(S) and resistance R(S), is connected in parallel with interferometer D1.