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Ready and Read Write Logic Disclosure Number: IPCOM000053235D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

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Desai, NM Shaughnessy, JP [+details]


System performance is improved by reducing worst-case read/ write signal delays, and also permitting the system to run at the speed of each I/O device rather than at the speed of the slowest one of the devices. a fast processor must interface with slow speed I/O devices and memories, the processor must be slowed down for data transfer operations. This slowing down can be accomplished by clocking the processor at the rate of the slowest device, or forcing a wait for speed matching with an active I/O device. Neither is an attractive route to follow from a performance standpoint.