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Self Aligned Via Less Interconnection Scheme Disclosure Number: IPCOM000053253D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

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Bhattacharyya, A [+details]


In the packaging of semiconductor chips, one conventional technique is to mount the chips on a substrate material. Frequently, to get high density circuits on the substrate, two or more layers of metallization are provided separated by a dielectric material.