Browse Prior Art Database

Self Aligned Via Less Interconnection Scheme

IP.com Disclosure Number: IPCOM000053253D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Bhattacharyya, A [+details]

Abstract

In the packaging of semiconductor chips, one conventional technique is to mount the chips on a substrate material. Frequently, to get high density circuits on the substrate, two or more layers of metallization are provided separated by a dielectric material.