Partially Good Array Packaging Scheme
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
This article describes a substrate and card arrangement scheme which, in conjunction with the selection of partially-good chips, minimizes the number of substrate designs. The scheme is designed to package partially good chips in a 1K by 10 bit format in which any one of the 10-bit lines may be bad. Normally, 10 different substrates would be required since there are 10 different wiring patterns required to wire the chip to the substrate pins depending upon which bit was bad.