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Low Capacitance Diffusion with Buried Contact Disclosure Number: IPCOM000053283D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

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Dockerty, RC [+details]


This process can be used to reduce junction capacitance (perimeter component) in MOSFETs. The capacitance is reduced because the surface concentration and junction depth of the field implant are larger than the values for the voltage threshold adjust, Vt, concentration and junction depth. The conventional semirecessed dielectric isolation 10 with P/(+)/ junction isolation regions 11 is provided within a silicon substrate 12 so as to isolate regions of silicon wherein MOSFET devices are to be formed. A P blanket ion implant is done to form P regions 13 for threshold adjustment, Vt. The gate silicon dioxide dielectric layer is formed upon the silicon surface of these regions by thermal oxidation. The process continues as follows: 1. A resist layer is deposited upon the silicon dioxide layer. 2.