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Hybrid Contact Metal Planarization Process

IP.com Disclosure Number: IPCOM000053303D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Reith, TM White, JF [+details]

Abstract

The fabrication of transistors which uses both a polysilicon base and emitter can result in severe vertical topography in the emitter contacts. Such processes employ polysilicon or oxide on the contact sidewalls, as shown in Fig. 1.