Browse Prior Art Database

Memory Application of Multiple Bit Chips

IP.com Disclosure Number: IPCOM000053305D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Aichelmann, FJ [+details]

Abstract

In memory systems using multiple bit output chips, the outputs from successful chips can not be simultaneously used within the same data group (ECC (error correcting code) word) without exposing the data to uncorrectable errors should a chip ``kill'' occur. The problem is avoided by buffering the multiple bit chip outputs through shift registers to enable the bits from the same chip to be distributed across subsequent data transfers. Each bit exiting from each shift register is consigned to a respective ECC word so that multiple bit failure in the same chip will not align within the same data group (ECC word).