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Shown in the drawing is an address true/complement generator wherein the number of active devices is minimized. which permits circuit density.
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In Line Word Address True Complement Generator
Shown in the drawing is an address true/complement generator wherein the
number of active devices is minimized. which permits circuit density.
Signal A, the values A and A of which are to be generated on output lines L
and L, is provided at input IN of in-line inverting stage I.
The levels on nodes B and C depend on the signal at input IN. When it is
equal to ``0'', the levels on B and C are low and high, respectively, and when it is
equal to ``1'', the levels on B and C are high and low, respectively.
Two identical output arrangements, one comprising transistors T4 to T6 and
resistors R4 and R5 and the other comprising transistors T8 to T10 and resistors
R7 and R8, provide adequate high and low levels on output lines L and L which
represent the true and complement values of signal A.
Due to this symmetrical arrangement both signals A and A are generated
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