Browse Prior Art Database

Memory Array Interface

IP.com Disclosure Number: IPCOM000053334D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Belyeu, SM [+details]

Abstract

This article describes an interface to allow a memory tester, such as a dynamic burn-in or functional tester, to exercise a memory array consisting of 480 memory modules. The interface specifications are a maximum signal overshoot of 15%, an undershoot of no more than 1 volt, a rise time of less than 40 nanoseconds, and an edge placement accuracy of plus or minus 15 nanoseconds. Since each driver is connected to a 1000 pf load capacitance and since there are long printed circuit lines between the drivers and the memory array, unusual circuit arrangements are needed to guarantee that these specifications are met.