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Address/ Timing Control Disclosure Number: IPCOM000053335D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

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Belyeu, SM [+details]


When using a microcontroller utilizing seven-bit instructions, the extra bit in program memory may be used to control a timing generator and a set of address counters in a memory tester. Fig. 1 shows a block diagram of an address/timing control circuit in a memory tester which controls a timing generator and provides addresses to a device under test (DUT). The address/timing control block requires two clock signals (clock 1 and clock 2) from a system clock and control logic and a specific instruction decode acknowledge CIDA) signal from the program and data memory.