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Power Saving Slave Latch

IP.com Disclosure Number: IPCOM000053404D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Carter, EL [+details]

Abstract

Level sensitive scan design (LSSD) solves testing and test-data generation problems at all levels of packagings, i.e., chips, boards, and system (1,2,3). In LSSD, it is customary to restrict the types of memory elements to random-access memories and shift register latch (SRL) stages. In certain applications, each SRL stage is configured with a linked pair of similar type D polarity-hold latches generally referred to as the Ll and L2 latches of the particular stage in (2,3).