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Minimizing Power Dissipation In Cascode Current Switch Arithmatic Logic Units

IP.com Disclosure Number: IPCOM000053407D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Carter, EL [+details]

Abstract

Cascode current switch arithmetic logic unit (ALU) circuits minimize power consumption and signal response delay (*). The number of cascode levels required for a particular circuit depends upon the functional complexity of the circuit. Generally, a large-scale integrated (LSI) chip incorporates circuits consisting of different numbers of cascode levels. A large power supply (e.g., 5.0 volts) is usually provided to accommodate the largest number of cascode levels (i.e., most complex circuit). It can be shown that as the number of cascode levels decreases in other circuits, however, a power dissipation penalty is incurred when using this same power supply level. Since many circuits on a chip require only one or two cascode levels, this penalty can be quite significant.