Browse Prior Art Database

Interconnection Test Arrangement Disclosure Number: IPCOM000053417D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue


Related People

Barnes, JD [+details]


The arrangement shown in the drawing utilizes circuits already available in logic modules or chips for testing the condition of the interconnections, particularly control lines. Portions of the circuitry for two modules 1 and 3, designated by dotted line boundaries, are shown.