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Method For Layout Of Memory Cell

IP.com Disclosure Number: IPCOM000053423D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Anantha, NG Bhatia, HS Denis, BA [+details]

Abstract

The chip layout shown in Fig. 1 maintains equal base widths in the two lateral PNP load transistors of the memory cell of Fig. 2 despite misalignment of the masks used in making the emitters and collectors. Similarly, the resistance between the emitter contacts and the respective emitter-base junctions also is maintained balanced despite misalignment of the emitter contacts. Such balancing increases the noise immunity of the cell and reduces false switching.