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Scheme For Improving Write Delay In Diode Coupled Memory Cells

IP.com Disclosure Number: IPCOM000053430D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Knepper, RW Petrosky, JA [+details]

Abstract

The techniques described apply to the design of bipolar random-access cells and, in particular, to the design of cells that are sensed and written via I/O diodes, such as Schottky barrier diodes. Two cells of this type are the Schottky-coupled cell and the complementary transistor switch (CTS) cell. Typically, when writing cells of this nature, it is necessary to pull the bit line high by a delta V of about 0.5-1.0 volt in order to switch a selected cell to the opposite state. In general a swing of about 1 volt on the bit line is required to guarantee writing in all cases if no additional circuit techniques are used to write the cell.