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Clock Generator With Barrier Implanted FET Device For Generating Negative Going Clock Signals

IP.com Disclosure Number: IPCOM000053432D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Varshney, RC [+details]

Abstract

FET devices in clock generators usually have a nominal threshold of the order of one volt. As source voltages for such FET devices are lowered below ground, such devices remain conducting for input signals between V(H) and ground. Barrier implanted FET devices raise the threshold to about 4 volts. Employing a barrier implanted FET at the end of a clock generator permits the source to be connected to -V(BB). Such barrier implanted devices provide an output signal which will switch between V(DD) or V(DD) -V(T) (depending upon the drive-in condition of a low device) to V(BB) for input signals between V(DD) and ground. The negative going output signal from the barrier implanted device may be used as a clock, or it may be used to drive subsequent circuitry which has nominal V(T) devices connected to -V(BB) devices.