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Bit Line Cascading In Semiconductor Storage Chips Disclosure Number: IPCOM000053445D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

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Arzubi, L Baier, E Knott, P Loehlein, WD [+details]


Fig. 1 shows a semiconductor storage with a cascading of the bit lines. In comparison with previous integrated semiconductor storages, only one buffer and one bit decoder are required for all the arrays on the chip. In spite of this, a useful signal of adequate magnitude is obtained, in particular for stores with a great number of cells. Also obtained is a considerably increased integration density.