Browse Prior Art Database

Switch Debounce Logic

IP.com Disclosure Number: IPCOM000053450D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Dobson, DR Hooker, RW Marchand, GV Proctor, MM Robb, MA [+details]

Abstract

Switch debounce logic is employed to prevent false indications from plural switches having different sampling time requirements. The switch is allowed to bounce for as long as the minimum time it takes to make three consecutive samples of the switch. The sample time is determined by individual switch characteristics.