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A double bit partitioner for CFET static programmable logic arrays utilizes fewer circuits and less power drain than the conventional circuit.
English (United States)
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Double Bit Partitioner
A double bit partitioner for CFET static programmable logic arrays utilizes
fewer circuits and less power drain than the conventional circuit.
Four NAND gates 1, 2, 3 and 4 of Fig. 1 are used to define a double bit
partitioner circuit. The conventional circuit of Fig. 2 requires two additional
inverters 5 and 6. Also, wires must cross four places in the conventional circuit,
while there is only one such crossing in Fig. 1. Thus the area of the Fig. 1 circuit
can be approximately one half the area of the conventional circuit.
In both circuits, three of the four NAND gates draw power for any
combination of inputs A and B. In the conventional circuit, either or both of the
inverters can be on, thus adding to the power drain of the circuit.
Both circuits also employ only a two stage delay. This is because if NAND
gate 4 changed state due to a change in the output of NAND gate 1, then NAND
gates 2 and 3 did not change states. Conversely, if NAND gate 4 changed state
due to a change in the output of either NAND gate 2 or 3, then the output of
NAND gate 1 did not change state. Hence, there are only two stages of delay.
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