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Rapid Linewidth Monitor Semiconductor Integrated Circuit Fabrication

IP.com Disclosure Number: IPCOM000053501D
Original Publication Date: 1980-Jan-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Lin, BJ Venkataraman, K [+details]

Abstract

This article describes a semiconductor fabrication process wherein, at each level in the semiconductor process (the recessed oxide level, the first polysilicon level, the second polysilicon level and the metal level), a series of linewidth and spaces (a pattern) is written according to groundrule dimensions for that particular level. The same pattern is repeated one above or below the previous pattern, as shown in Fig. 1, but the patterns are displaced longitudinally from the previous pattern by a preset distance. When the edges are coincident between two adjacent patterns, the corresponding setback in design is a measure of total etch bias of the line. The setback can be adjusted to be an integer multiple of the pattern-generation grid minimum which is 1/8 micrometer at present for a vector scan electron-beam system.