Address Decode Circuit, Programmable and Useful for Chip Select
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12
A cross-coupled address buffer circuit is modified to decode chip-selection address by hardware grounding of preselected output lines such that clocking is enabled past the latch status only when all lines in a logic element are not grounded by the combined status of the input signals and the hardware grounds. The hardware grounding can be by solid-state switch, thereby providing field programming. The circuit is inherently compatible with a system employing the unmodified address buffer circuits.