Programmable, Expandable Interrupt Controller
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12
A host processor is interrupted by signals from a universal interface, to which gating is added to activate the universal interface in response to an interrupt-acknowledge signal from the host processor. This provides more than eight interrupt signals. The number of interrupt signals to which the system responds is further expanded by employing an I/O expander in communication with the universal interface.