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Multiplexed CODEC Using Shift Register Storage

IP.com Disclosure Number: IPCOM000053558D
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Crouse, WG Heinz, MT Markey, HG Parr, JW Williams, TA [+details]

Abstract

A shift register storage is disclosed for a multiplexed voice encoder/decoder (CODEC) which enables the cyclic storage of a plurality of intermediate values calculated by the CODEC for each respective voice line and which applies a predetermined delay to the execution of each respective computation, as required by the CODEC algorithm.