Browse Prior Art Database

ESD Hold Off Scheme

IP.com Disclosure Number: IPCOM000053588D
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Willson, DJ Zimmer, EA [+details]

Abstract

High speed electronic circuits such as used in computers are susceptible to errors induced by electrostatic discharges (ESD). In order to determine the ability of a computing device to withstand such discharges without generating errors, it is common to test a device by injecting static discharge pulses at a variety of points at increasing voltages until a non-recoverable error occurs. Since the particular state of the device may determine its susceptibility to error, thousands of pulses are injected at each point to assure that a wide variety of states encountered in normal operations have been evaluated.