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Polarity Selectable Run Scan Synch Circuit Disclosure Number: IPCOM000053633D
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12

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Related People

Bucelot, TJ Feder, JD [+details]


An on-chip, polarity selectable Run/Scan circuit is described for the control of data flow in Josephson logic chips during both testing and normal operation. The circuit produces appropriate logic level signals to control the operation of the on-chip latches in the normal mode (Run) or in LSSD (level sensitive scan design) mode (Scan). The input to the circuit is provided by a DC current source, which can be a room-temperature device. The arrival of the input current need not be synchronized to the chip power cycle, as this circuit provides synchronization. Single-cycle (SC) or multiple-cycle (MC) operations are selected by the magnitude of the input current, while the polarity of an SC output is determined by the polarity of the input. The chips' primary inputs will be DC, whereas the power will be bipolar.