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Word Line Decoder Disclosure Number: IPCOM000053636D
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12

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Related People

Chao, HH Wordeman, MR [+details]


An improved word line decoder circuit is designed to relax the operating voltage limitation of a high density single-polysilicon one-device field-effect transistor (FET) random-access memory (RAM), whereby the associated gate-bounded junction breakdown problem is avoided.