Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12
This article describes a high performance dynamic decoder circuit that provides an output voltage level greater than the supply voltage. The high output voltage reduces the selected switch resistance and therefore the time required for a differential voltage to pass through it. The circuit operates even with large decoder capacitance. A diagram of the decoder circuit is shown in the drawing. During the precharge part of the selection cycle, PC4 is high and CS4 is low. Nodes 2, 3 are precharged high through devices 4, 5, respectively. This is a departure from a more conventional approach where the decoder output only goes high on the selected decoder. The decoder is activated by CS4. Prior to CS4 rising, the Y addresses must be valid and PC4 must have been turned off.