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Programmable Logic Array Physical Implementation

IP.com Disclosure Number: IPCOM000053655D
Original Publication Date: 1981-Oct-01
Included in the Prior Art Database: 2005-Feb-12

Publishing Venue

IBM

Related People

Authors:
Cases, M Moore, VS Stahl, WL Thoma, NG [+details]

Abstract

Programmable Logic Arrays (PLAs) are built in a smaller physical area than heretofore possible. The drawing illustrates interconnections of various elements in a representative PLA. The PLAs are implemented using a two-micron single polysilicon in-metal out-cell. Here, the same cell is being used for an AND array as well as an OR array by the use of a polysilicon contact cell to match the AND metal output to the OR polysilicon input. Depletion load device cells are placed at the other end of the AND output lines. The OR depletion load devices are contained in another cell which essentially has the load device contained within an output contact-to-contact adapter.